This invention is related to integrated circuit devices and in particular to volatile random access memories, commonly known as dynamic random access memories (DRAMs).
A DRAM is a type of random-access memory integrated circuit that in the most common commercial implementation stores each bit of data in a separate capacitor coupled to a transistor within the integrated circuit. The capacitor can be either charged or discharged. The states of charged or discharged are interpreted as values of a bit, i.e. ‘0’ and ‘1’. The one-transistor one-capacitor cell has been the most commercially used memory cell used in DRAM devices for the last 30 years. Lithographical scaling and increasing process complexity have enabled the number of bits of storage in a DRAM to quadruple about every three years, however the individual memory cells are now so small that maintaining the capacitance of each cell, and reducing charge leakage, are significant problems inhibiting further size reductions.
In response to these challenges and other problems, alternative DRAM memory cell architectures have been proposed. One such approach is known as a floating body DRAM (FBDRAM). The FBDRAM is a single MOSFET built on either a silicon-on-insulator (SOI) (Okhonin, Int. SOI Conf., 2001) or in a triple-well with a buried N-implant (Ranica, VLSI Technology, 2004). The transistor's body forms a capacitor against the insulated substrate. The technology has yet to solve its data retention issues, particularly at scaled dimensions.
Another approach to a new DRAM architecture is based on the negative differential resistance behavior of a PNPN thyristor. In these designs an active or passive gate is used. For example, a thin, capacitively coupled thyristor described in U.S. Pat. No. 6,462,359 uses a lateral PNPN thyristor on a SOI substrate with a coupling gate for increased switching speed. Unfortunately, the lateral aspect of the design, together with the need for a gate, results in a memory cell substantially larger than a conventional one-transistor one-capacitor DRAM cell structure.
Liang in U.S. Pat. No. 9,013,918 describes a PNPN thyristor cell constructed on top of a silicon substrate and operated in forward and reverse breakdown region for writing data into the cell. Unfortunately, the use of epitaxial or CVD semiconductor layers at the backend of the standard CMOS process, adds thermal cycles and etching steps that can degrade performance and yield of other devices earlier formed on the same substrate. In addition, PNPN devices operated in the breakdown regime pose challenges in process control and power consumption.
What is needed is a DRAM memory cell smaller than the conventional one-transistor one-capacitor, that is easily scalable below 20 nm design rules, is compatible with standard bulk silicon processing, and consumes less power, both statically and dynamically.